There are several types of field effect transistor designs. Most common transistor technology is CMOS FET (Complementary Metal Oxide Semiconductor Field-Effect Transistor). But due to trend in decrease in technology node, a new field-effect transistor technology has appeared. This technology is called as FinFET and it appeared after 25nm technology node and it started to be utilized in lower nodes.
What is CMOS FET Technology?
Before continuing with FinFET, lets start with CMOS process that caused appearence of FinFET technology. CMOS corresponds to a process that is able to fabricate both NMOS and PMOS transistor within same design. The standard CMOS process is given in following figure. As it is known, if Gate voltage is large (or small) enough in NMOS (or PMOS) transistor, channel will be formed between Source and Drain. As required voltage differences are satisfied, current between Source and Drain can be controlled through Gate voltage.
The width of Gate node is indirectly determines the technology node that we are talking about. After a certain value, the process becomes limited by the lithography process that is one of the most important steps in CMOS fabrication. Another important parameter in CMOS technology is thickness of oxide between Gate material and substrate. Decreasing the thickness is adventageous in terms of power consumption because the applied voltage will be decreased. But oxide with lower thickness results in higher leakage and probably transistor break-down. These two concerns are main challenge in IC Design indurstry.
Standard CMOS technology is planar and easy to fabricate. It does not require too many processing steps. In standard CMOS process, gate has contact on single side of the channel. In FinFET technology, contact will be on 2, 3 or 4 sides of channel.
As FinFET structure in figure, source-drain structure forms a fin therefore it is named as FinFET. It was studied by University of California Berkely in 2011 for the first time. In 2002 TSMC, that is one of the largest foundary in terms of volume, annouced 25nm 0.7V FinFET process. This process is named as Omega-FinFET and gate covers Fin on all sides.
Apart from this, Intel used tri-gate design that is based on coverage of gate on three sides of channel. The physical view is not same with Omega-FinFET but it has some similarities.
Why Do We Need Lower Technology Nodes?
As we described MOSFET and FinFET, a question may arise: Why do people are working on technology node development?
First apparent answer of this is speed. Speed of transistors depends on the gate capacitance and therefore it depends on gate area. If gate area is decreased, then capacitance will be decreased with same ratio. Due to this, larger speed can be achieved.
Second answer is cost and area. If minimum transistor size is decreased, then area of a single transistor will be decreased. Then you can fit larger number of transistors into same area. Therefore you can add more functionality inside the same area. Hence cost per transistor will be decreased.
Third answer is power consumption. This is not a direct result of technology node development. Because it is related to oxide thickness. If thickness decreases, lower gate voltage is required for channel formation. However, decreasing thickness of oxide will cause increase in oxide capacitance. Some solutions are developed for this problem as well. Instead of using Silicon dioxide as oxide layer, different low-K dielectric materials are implemented.
FinFET transistors are easier to fabricate and due to this, it is used by most of the faundaries. The enhancements that are listed above are benefical for digital designs. Because speed and functionality are main concerns of digital design. Whereas in most of the analog design, researchers are still using standard CMOS process because leakage is more important in analog designs and in analog designs different concerns are considered.